Integrated circuits may comprise a plurality of devices, like for instance transistors, or conductive lines or contact structures arranged in a regular pattern having for example an array-like geometry. The pattern may show small device dimensions and small pitches of the devices in order to save space on the wafer or carrier surface and costs. Devices, conductive lines or contact structures may be arranged in patterns having different geometries in different planes of an integrated circuit. For example, a pattern in a first plane may show regular line geometry, whereas a pattern in a second plane may show a matrix or checkerboard geometry. Transforming a first pattern into a second pattern (e.g., contacting devices, conductive lines or contact structures in different planes being arranged in different patterns) is challenging especially at small device dimensions and at small pitches near the minimum lithographic feature size obtainable by a specific technology.
Integrated circuits may comprise devices in an array region as described above and devices in a peripheral region. For example, an integrated circuit may comprise memory cells arranged in an array region and devices, like transistors or others, which are configured to control read and write operations of the memory cell array, in a peripheral region. A need exists for a common processing of structures in the array region and in the peripheral region (i.e., for a processing being effective in both regions).